Title Off-Chip Bandwidth: The New Wall in The Multicore Era

Mohamed Zahran

Abstract

With the number of on-chip cores consistently increasing, we would expect a corresponding increase in performance. However, there are several “walls” in the face of this ultimate goal. For single core architecture, we had the memory wall. In this talk I will discuss the new wall in the multicore era, which is the off-chip bandwidth requirement. These cores need to be fed with data and instructions, and need to spill data back to the memory or off-chip caches. This puts a lot of pressure on buses, memory ports, and the not-very-scalable pads. I will propose several techniques that we developed to decrease off-chip bandwidth requirements with little hardware cost and minimal, if at all, impact on overall performance.

Bio

Mohamed Zahran received his Ph.D. in Electrical and Computer Engineering from University of Maryland at College Park. He worked as a research scientist at The George Washington University for a year, before joining the Electrical Engineering department at City University of New York. His research interest spans several aspects of computer architecture, such as microarchitecture, memory system design for manycore architectures, and power-aware architecture. Zahran is a senior member of IEEE, senior member of ACM, the American Association for the Advancement of Science (AAAS), and Sigma Xi.

courses/sigsys/zoran.txt.txt · Last modified: 03/14/2009 13:43 by sigsys
  • 213 Smith Hall   •   Computer & Information Sciences   •   Newark, DE 19716  •   USA
    Phone: 302-831-6339  •   Fax: 302-831-8458